In this paper, is shown an approach to realize leapfrog structures obtained from proto-type passive RLC ladder filters using current differencing buffered amplifiers (CDBA) as active elements. The use of the CDBA's provides advantages that the realization procedure is simplified and the number of active components required is reduced. The approach is quite suitable for the realization of band-pass ladder filters, which generally requires a complicated structure to simulate LC series and/or parallel resonant branches by the conventional opamp-based leapfrog filters. A simple circuit configuration of the CDBA suitable for high frequency and low power supply voltage applications is also presented. As design examples, a fifth-order Butterworth lowpass ladder filter and a sixth-order Chebyshev bandpass ladder filter are designed. The effectiveness and the correctness of the proposed approach and the characteristics of the proposed filters are verified and examined through computer simulation.

An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

This letter proposes a simulation of an input part of an LCR filter. The proposed method used voltage followers as an active element. As an example, a realization of a 3 MHz third-order maximally-flat filter is presented.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

An integrator is quite a suitable active element for high-speed filters. The effect of its excess phase shifts, however, is severe in the case of high-Q filter realization. The deterioration due to the excess phase shifts cannot be avoided when only integrators are used as frequency-dependent elements like in leapfrog realization. This paper describes a design of second-order high-speed and high-Q filters with low sensitivity to excess phase shifts of integrators by adding a passive RC circuit. The proposed method can drastically reduce the effect due to the undesirable pole of an integrator, which is the cause of the excess phase shifts, compared to conventional filters using only integrators. As an example, a fourth-order bandpass filter with 5-MHz center frequency and Q=25 is implemented by the proposed method on a monolithic chip. The results obtained here show quite good agreement with the theoretical values. This demonstrates effectiveness of the proposed method and feasibility of high-speed and high-Q filters on a monolithic chip.

A building block for widening an input range under low power-supply voltages is proposed and the block is used in a popular linearization technique for voltage-to-current converters. The block employs two MOSFETs each of which actively works when and only when the other is in cutoff region. Accurate level shift circuits for the control of the MOSFETs enable such exclusive operation. Simulation results show that the complementary MOSFETs perform as an equivalent MOSFET without any cutoff region. It is also confirmed that the novel linear voltage-to-current converter is effective for not only a wide input range but also low-power consumption.

This paper proposes an extension of a conventional current conveyor (CC) concept and its applications. A relaxation of the definition of a conventional CC makes a CC simple. A novel current conveyor named extended current conveyor (ECC) is introduced. An ECC keeps the most significant feature of a CC, i.e., a CC is combination of a VCVS and a CCCS. On the other hand, the other conditions are relaxed. All terminals of the ECC are allowed to have offset voltage and offset current. An ECC usually has a simple structure with a small number of MOSFETs thanks to the relaxation of the conditions. Some circuit configurations for the ECC which have various characteristics are shown. An NIC and OTAs are realized using ECCs. Validity of an ECC is confirmed through HSPICE simulation.

A simple but efficient method to improve readability of discrete pseudo time-frequency representations (TFRs) of nonstationary signals by the reassignment of the representations in discrete frequency dimension is presented. The method does not rely on the nonzero time derivative of the window function employed in the estimation of pseudo TFR. This property of the reassignment method is advantageous because the method can provide an improved readability in the situation when a known reassignment method is unefficient. The reassignment of the TFRs of corrupted signals is discussed. Numerical examples are included to illustrate the performance of the proposed method.

A design of current-mode continuous-time filters for low voltage and high frequency applications using complementary bipolar current mirror pairs is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integration. Since the filters are based on the integrator type of realization, the proposed method can be used for a wide range of applications. The frequency of the filters can easily be changed by the DC controlling current. A fifth-order Butterworth and a thirdorder leapfrog filter with tunable cutoff frequencies from 20 MHz to 100 MHz are designed as examples and simulated by SPICE using standard bipolar parameters.

The local moment functions for discrete Wigner trispectrum are examined in ambiguity and in time-frequency domain. A concept of multiple and multidimensional circular convolution in frequency domain is introduced into the discrete Wigner higher order time-frequency signal representation of any order. It is shown that this concept based on the 1st order spectra of the signal offers an insight into the properties of inconsistent local moment functions and their representation both in ambiguity and time-frequency domain. It allows to prove that midfrequency crossterms of a multicomponent signal can not be removed by any generalized 4th order ambiguity function which employ kernel function in the ambiguity domain. It is shown, that the concept of multiple convolution in frequency domain can lead to the crossterm-reduced discete time-frequency representations of any order

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. Two algorithms are given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using the mixed integer programming (MILP). Utilization of common expressions in Hartley's technique widens the CSD coefficient space. Thus the MILP may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

In this paper, DSPs, of which memory addresses are pointed by special purpose registers (address registers: ARs), are assumed, and methods to derive an efficient memory access pattern for those DSPs proposed. In such DSPs, programmers must take care for efficient allocation of memory space as well as effective use of registers, in order to derive an efficient program in the sense of execution period. In this paper, memory addresses and AR update operations are modeled by an access graph, and a novel memory allocation method is presented. This method removes cycles and forks in a given access graph, and decides an address location of variables in memory space with less overhead. In order to utileze multiple ARs, methods to assign variables into ARs are investigated. The proposed methods are applied to the compiler for DSP56000 and are proved to be effective by generated codes for several examples.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

As current-voltage characteristics of GaAs MESFET differ from those of BJT and MOSFET and n-channel FET is only practically in use, the development of GaAs MESFET analog integrated circuits is left behind. In this paper, two circuit techniques to improve the performance of GaAs MESFET analog circuits are provided. The one is to realize a high impedance active load circuit which dose not need CMFB (Common Mode Feed Back) to achieve stable DC biasing point. The other is to cancel the harmonic destortion caused by nonlinear characteristics of GaAs MESFETs. As an application example of the proposed circuits, biquad low-pass and band-pass filters are realized and simulated by HSPICE to verify the validity of the proposed method.

Mixed Quasi Newton simulation algorithm that is capable of calculating analog circuits containing mixed level of element models is presented. Conventional circuit simulators usually apply Newton method to solve nonlinear system equations resulted from circuit equations. At each Newton iteration step, it is necessary to reevaluate the Jacobian stamp of circuit elements. However, obtaining the Jacobian stamp of elements described by complex behavior models is a computationally expensive process. To reduce the number of Jacobian evaluations, we combine Newton method and Quasi-Newton method as a new updating scheme. The simulation results show that our algorithm can reduce the number of Jacobian evaluations and improve the simulation time, particularly when simulating circuits containing many behavior model elements.

In this paper, current-mode integrators which consist of only n-channel depletion-mode FET and their application to filters are presented. Lossy integrator is simply realized with a capacitor and a grounded gate FET. Lossless integrator can be obtained by providing a lossy integrator with a positive feedback. To do this, multi-output current mirror is proposed. To reduce 2nd-order harmonic and THD of the filter, unbalanced/balanced conversion circuit is proposed. As an application example, 3rd-order leapfrog low-pass Chebyshev filter is simulated with GaAs MESFET process parameters. Simulation results show good performances.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

A high frequency MOSFET model is presented. This model takes into account the electron mobility reduction due to the normal and parallel fields. By using a frequency power series, an analytic second order expression for the intrinsic admittance parameters is obtained. This intrinsic admittance model is first simplified and then completed by the external elements, measured, or calculated in the case of the high frequency lateral type structure. The proposed model shows that the two-field-dependent mobility effect reduces the unilateral power gain by maximum 2 dB compared to the one-field-dependent mobility and constant mobility models. The proposed model gives a good prediction of the scattering parameters measured from 50 to 200 MHz. The average deviation of the calculated unilateral power gain from the measured values is 1.86 dB.

This paper discusses the input range limitation problem in a track-and-hold circuit and the compensation method using a bootstrapped switch. A bootstrapped switch with an additional control circuit is proposed to compensate charge loss in conventional bootstrapped switch circuit. Simulation results using 0.18-µm CMOS process parameters show that the proposed circuit reduces the bootstrap capacitance down to 25% for the conventional circuit.